Successful use of the Mentor DRCs on PCB designs using padcap Geometries
Utilitek Systems, Inc.
The design rule checks (DRCs) that are built into Mentor Layout will completely check a design. However, it is not obvious that to completely check for shorts and opens, Check Traces is not sufficient. Despite the functions that their names imply, both Check Pins and Check Components play a role in looking for shorts and opens. In fact, it is quite possible to get a clean Check Traces and still have shorts in your design.
This problem is especially severe for Mentor users who build their SMT geometries with pad cap or static breakouts. Several of our customers who use our PCB design service use this technique for building SMT geometries. This technique essentially turns a SMT component into a through hole component by constructing the SMT land out of an added padstack or a set of polygons and then adding breakouts and through hole pins to the geometry to form the breakout "vias". The pins of the geometry, as Layout sees them, are the through hole pins in the geometry and not the SMT lands. Using this technique, if the proper DRCs are not run in the proper order, it is very easy to send a board to the fab house that has shorts in it.
An example of a pad cap discrete is shown below:
It consists of three main elements.
The SMT lands that the device is soldered to. These are usually constructed of polygons on the pad, pastemask, and soldermask layers or of added geometries. I will refer to these SMT lands as the polypads.
The through hole pins that form the via for the pad cap geometry. This is a real pin and is a through hole padstack. I will refer to this element as the PTH pin.
The path of copper from the SMT land to the PTH pin. This is usually a path on the layer pad. I will call this path the stringer.
Using pad cap geometries has advantages and disadvantages.
Ease of testpoint generation for ICT
Autorouting and manual routing is much easier
Extra, unnecessary holes in the PCB
Placement density suffers due to PTH pins built into geometry
Extra thought, planning and effort goes into building geometries for use in 2 sided placement
DRCs built into Layout
The Check Traces function in Layout does not check certain clearances that one might assume that it would. For example, it does not check the clearance between a pin and copper that is unrelated to the routing, such as a polygon. Believe it or not, Check Components is supposed to cover this clearance check, if you have the proper options set when you run it. Check Traces also does not check the clearance between two pins. Check Pins performs this check. Therefore in any design, whether padcap or not, you must run Check Components, Check Pins, and Check Traces in order to be assured of a PCB design that does not have clearance errors. When running Check Components, you must have the options set as shown below in order to be effective:
A padcap design is particularly vulnerable to clearance problems that Check Traces will not pick up. The clearances from the PTH pins in a padcap geometry to the stringers and polypads of other nearby padcap geometries can be very easy to violated, especially in a design with components on both sides. An example appears below in which a 1206 is on top and a 0805 is on bottom.
The PTH pins from the 0805 are shorted to the polypads of the 1206. Check Traces will not pick up this error. Only Check Components will.
Unfortunately, Check Components will give an error within a padcap geometry itself if it is not constructed properly. From Layouts point of view, the stringer is an extraneous piece of copper that is touching a real pin: the PTH pin. Running Check Components with the Pin to copper checking option yields an error within the geometry itself due to this. The result is that every padcap geometry on the board is in error. Sorting through the thousands of errors that result in order to find the real errors such as that of the 1206/0805 problem is nearly impossible.
Approaches to getting complete checking on a padcap PCB design
We found two basic approaches for trying to eliminate the errors that are flagged within a padcap geometry while still keeping the errors between padcap geometries. The first was to manipulate the geometry so that while placing the PCB the stringers were moved to a layer that was not checked. For this purpose, we created a pad_to_via layer and some userware that ran in Librarian that opened every padcap geometry and moved the stringer from the pad layer to the pad_to_via layer. Since the pad_to_via layer was not a checking layer, this worked well during placement except for the situation when a PTH pin from another geometry was over the area where the stringer would normally be. However, since the stringers were typically very short, when this occurred the polypad would usually be shorted too and the error would be revealed by running Check Components. Before starting into routing the librarian userware would have to be run again and the stringers moved back to the pad layer. This had to be done so that routed traces would not be run over the stringer locations. This method had the drawback of having two separate checking procedures, Check Components with the stringers on the layer pad_to_via, and Check Traces with the stringers on the layer pad. To get between the two procedures the user would have to exit Layout, enter Librarian, run the userware, exit Librarian and enter Layout again. This method proved to be effective but time consuming.
The second method was to adjust the construction of the padstack geometry and the termination points of the stringer on the PTH pin so that Check Components did not report an error. It turns out that if the termination point of the path (the center of the radius at the end of the path) is outside the diameter of the drill in the PTH pin, but still inside the diameter of the circle forming the land of the pin (the circle on layer signal and pad_1 and pad_2) no error is detected from the PTH pin to the path that forms the stringer by Check Components. The figure below shows this situation:
The thousands of errors that resulted form errors within each padcap geometry were eliminated and it is now easy to look at the remaining errors from Check Components. These errors are the errors from the polypads and stringers to the PTH pins of other padcap geometries and are the real errors we are looking for.
We prefer to construct the PTH pin and stringer so that the center point of the path forming the stringer is just inside the circle on pad_1 forming the land of the PTH pin.
Overall, this second method has the advantage of not requiring the user to switch between Layout and Librarian several times and is the approach that we recommend to our customers.
All Boardstation users need to be aware that a clean Check Traces does not guarantee that a PCB design is error free. In order to get a complete DRC check, Check Pins and Check Components must be run also.
On padcap designs the user must take special measures in order to use Check Components effectively and find the shorts from the polypads and stringers to real PTH pins. There are several approaches to achieving this, but we have found that terminating the paths that form the stringers in a strategic location is the approach that we prefer.